A VCO-buffer circuit is mainly used as interface between a Voltage Controlled Oscillator (VCO) and counters in a PLL (Phase Locked Loop). The purpose of the VCO-buffer circuit is to shift the level of the VCO output voltage to a level suitable for the counters operation so as to adjust the duty cycle of the counters. Here the VCO-buffer circuit for Ring VCO (hereinafter referred to as RING/VCO) is used as an interface.
One conventional VCO provides a VCO buffer cell that comprises a differential pair of transistors and a current mirror circuit. The differential pair of transistors receives input terminals and generates a differential voltage swing in response to the input signals. The current mirror circuit is operably coupled to the pair of transistors and is configured to receive a first external reference current and provide a mirrored current to an active one of the transistors. The VCO circuit provides high-speed consistent output but uses additive circuitry for the purpose and therefore causes an increase in the overall device area, which is undesirable in area specific Voltage Controlled Oscillators.
Schematics of conventional VCO and VCO buffer circuits are shown in FIG. 1. The Ring Oscillator shown is a three-stage oscillator circuit. The three stages of the oscillator are the inverter stages. The oscillation frequency of the Ring is determined by the delay in the inverting stages. The VCO buffer shown is coupled between the VCO and the counters in the Phase Locked Loop. As shown in the figure it is a three input (IN1, IN2, IN3) device powered by a higher voltage supply DVDD and connected to ground at DGND. It generates an output PHI that serves to shift the level of the VCO output voltage to a level suitable for the counters operation so as to adjust the duty cycle of the counters.
The following symbols are used hereafter for the analysis of the VCO buffer circuit:    Vthn=Threshold Voltage of NMOS transistors    Vthp=Threshold Voltage of PMOS transistors    Kn=Transconductance Parameter of NMOS transistors    Kp=Transconductance Parameter of NMOS transistors    VIN=Input voltage to the stages for loading the RING.    DVDD=Digital Supply Voltage input to the VCO and VCO-buffer circuit.    Vo1h=Minimum High output voltage.    Vo1l=Maximum Low output voltage.    Vm=Peak value of the input voltage.
The nodes of the RING are loaded by a stage as shown in FIG. 2, which is a transistorized circuit formed by PMOS MS1P1 and NMOS MS1N1 or by a stage as shown in FIG. 3, which is formed by PMOS MS2P1 and NMOS MS2N1, wherein the input to NMOS is VIN and a bias signal BIAS is applied to the PMOS transistor. The following cases are considered for loading the VCO circuit (FIG. 1) by the stages shown in FIGS. 2 & 3.Case (1) when VIN=0; Vo1h=DVDD−Vthp  1.1Case (2) when VIN=Vm;Vo1l=(DVDD−Vthp)+((2*βs1n1)/βs1p1)*(Vm−Vthn)−((2*βs1n1)/βs1p1)*(Vm−Vthn)*sqrt(1+(βs1n1*(Vm−Vthn))/(βs1p1*(DVDD−Vthp)))  1.2where, βs1n1=Kn*(W/L)s1n1andβs1p1=Kp*(W/L)s1p1.
If the digital supply changes by a small amount ΔDVDD, then the corresponding change in Vo1l is given by:ΔVo1l=ΔDVDD(1−1/sqrt((1+(βs1p1*(DVDD−Vthp))/(βs1n1*(Vm−Vthn)))  1.3
If the digital supply changes by a small amount ΔDVDD, then the corresponding change in Vo1h is given by:ΔVo1h=ΔDVDD   1.4
For the circuit shown in FIG. 1;Case (1) when VIN=0; Vo2h=DVDD  1.5Case (2) when VIN=Vm; Vo2l=0  1.6
If the digital supply changes by a small amount ΔDVDD, then there is no change in Vo2l. The change in Vo2h is given by:ΔVo2h=ΔDVDD   1.7
FIG. 4 shows a conventional VCO-buffer circuit. The operation of the circuit is discussed as follows:Case 1: When IN1=0, IN2=Vm;Case 2: When IN1=Vm, IN2=0;Case 3:When IN1=Vm, IN2=Vm;Case 4:When IN1=0, IN1=0.
Case (1): In this case the voltage at node VBUF_MIR_OLD is Vo1h (equation 1.1) that causes PMOS MP2 to be switched off. Further, since IN2=Vm, the node VBUF_OLD discharges to zero volt.
Case (2) In this case the voltage at node VBUF_MIR_OLD is Vo1l (equation 1.2) that causes PMOS MP2 to be switched on. Further, since IN2=0 volt, the node VBUF_OLD charges to DVDD.
Case (3) In this case the voltage at VBUF_MIR_OLD node is Vo1l (equation 1.2) that causes both the PMOS MP2 and NMOS MN2 to be switched on and the voltage at VBUF_MIR_OLD is determined by the relative sizes of the transistors MP2 and MN2.
Case (4) In this case both PMOS MP2 and NMOS MN2 are switched off. The voltage at node VBUF_MIR_OLD is determined by the value of VBUF_MIR_OLD, before IN1 and IN2 both become zero volt.
As shown in FIG. 4 transistors MN1 and MN2 of the buffer load the VCO at two inputs (nodes IN1 and IN2). A dummy transistor MN3 is used to load input IN3 for providing balanced load distribution on the three nodes of the VCO. Symmetric loading is necessary so that the oscillation amplitude at each of the three nodes is the same, which in turn improves the phase noise performance of the VCO.
The capacitances by which these nodes are being loaded (by the buffer only) are the gate to source capacitance (Cgs) and the gate to drain capacitance (Cgd) of the transistors MN1, MN2 and MN3. During each oscillation cycle IN1 or IN2 or IN3 oscillate from zero volt to Vm and then again to zero volt (Loads are being charged and discharged). Here, charging and discharging of the Gate to Drain Capacitances of transistors MN1, MN2 and MN3 are discussed, because the amount of charge on these capacitors depends upon the value of DVDD.
Assuming the digital supply to be at DVDD, the VCO-buffer circuit operates for the following input-output parameters:    When IN1=0, the voltage at node VBUF_MIR_OLD is Vo1h (equation 1.1);    when IN1=Vm, the voltage at node VBUF_MIR_OLD is Vo1l (equation 1.2);    when IN1=0 and node VBUF_MIR_OLD at Vo1h the charge on the drain to gate capacitor of MN1 is given by:Qicgd=Cgd*(Vo1h−0)  1.8
When IN1=Vm and node VBUF_MIR_OLD at Vo1l (equation 1.2) charge on drain to gate capacitor of MN1 is given by:Qfcgd=Cgd*(Vo1l−Vm)  1.9
If the oscillation frequency is fo then the average current per cycle used to charge this capacitor is given by:
                                          lavch            ⁢            1                    =                                    (                              fo                /                2                            )                        *                          (                              Qfcgd                -                Qicgd                            )                                      ⁢                                  ⁢                                            =                        ⁢                          >                        ⁢                          lavch              ⁢              1                                =                                    (                              fo                /                2                            )                        *                          Cgd              ⁡                              (                                                      Vo                    ⁢                    1                    ⁢                    l                                    -                  Vm                  -                                      Vo                    ⁢                    1                    ⁢                    h                                    +                  0                                )                                                                1.10      
The direction of this current is through drain to gate capacitor of transistor MN1into the RING. Further, the current directly adds to the current going into the RING and depending on the amount of current going into the RING the oscillation frequency of the VCO is fixed.
Assuming that the digital supply changes from DVDD to DVDD+ΔDVDD, then it is observed that the average current by which the capacitor is being charged each cycle changes from (fo/2)*Cgd(Vo1l−Vm−Vo1h+0) to (fo/2)*Cgd(Vo1l+ΔVo1l−Vm−Vo1h−ΔVo1h+0). The change in average charging current lavch1 is given by:Δlavch1=(fo/2)*Cgd(ΔVo1l−ΔVo1h)  1.11
Applying similar analysis to charging of drain to gate capacitor of transistor MN2, which is driven by node IN2 we can say that average current by which this capacitor is being charged each cycle changes from (fo/2)*Cgd(Vo2l−Vm−Vo2h+0) to (fo/2)*Cgd(Vo2l−Vm−Vo2h−ΔVo2h+0).The change in average charging current lavch2 is given by:Δlavch2=(fo/2)*Cgd(−ΔVo1h)  1.12
From equations 1.11 and 1.12 we note that |Δlavch2|>>Δlavch1.
This implies that the current that is going into the RING for a particular control voltage increases by Δlavch1+Δlavch2. Since both the quantities Δlavch1 and Δlavch2 are negative we can also say that the current that is going into the RING for a particular control voltage reduces by |Δlavch1|+|Δlavch2|. As a result the oscillation frequency reduces and when there is negative jump on the digital supply it can be proved by a similar argument that the oscillation frequency increases. A similar analysis can be done for the discharging current of the gate to drain capacitances of the transistors loading the RING.
The noise on the digital supply causes the oscillation frequency of the RING to vary which is mainly due to the changes in the charging and discharging currents of the gate to drain capacitances of the transistors loading the RING, which is undesirable for the operation of the VCO and VCO-buffer interface.
Thus, a need is felt for VCO buffer circuit that reduces the variation in oscillation frequency of the ring oscillator.